Historically, the semiconductor industry has relied on personal computer (PC) sales to drive growth. However in the recent past, semiconductors have found a home in the world of consumer electronics, where embracing newer technologies has become a fashion statement. As a result, consumer electronics products have a short shelf life and time-to-market is a key factor in the success of products. Another consequence of the surge in consumer electronics is the demand for more integrated semiconductor technologies with smaller geometries as well as need for better battery life. These trends bring in a need for advanced design techniques where designers often source IP (Intellectual Property) blocks consisting of RTL (Register Transfer Level) design descriptions from various third party vendors and also reuse IP blocks across various SOCs. Often the SOC architect is not aware of the internals of an IP block functionality.
System-On-Chip (SOC) designs are large and complex, frequently reaching sizes in excess of 50 million gates. As a result, when a new or enhanced application is to be addressed by a new design, the new design is most often a modification of a previous SOC design. Typically, an engineering organization attempts to use as much of the previous design as possible in order to save time, resources, and expense, however last minute modifications are often made—some including the addition of IP blocks—with the result that power distribution is compromised and/or some nets are lengthened due to placement and congestion issues thereby compromising performance. In some cases, signal congestion will actually prevent a design from successfully routing. Some of these negative effects are due to the existing hierarchy structure which drives both placement and power distribution.
In the case where routing congestion makes nets too slow, or in some cases prevents successful routing altogether, it then becomes essential to dissolve the hierarchy of some of these IP blocks and merge portions of them with other logic for better routing. Given that designers will not be aware of the logic in most third party supplied IP blocks, a manual restructuring of IP blocks is quite error prone and lengthy. Also, with a focus towards low power design for better battery life, it is important to place various IP blocks and logic into different voltage and power domains based on the active functionality of a handheld device. These multiple voltage domains require designers to again restructure the design hierarchy and group functional design elements so that logic within the same voltage domain are preferably within the same hierarchy. This is also a manual step today and is quite error prone.
Therefore, it would be useful to have an automated way to restructure the hierarchy of an SOC design in order to move design elements with the same supply voltage closer together and/or move functions to reduce congestion for better routing and/or shorten the length of timing-critical nets.